1. Field of the Invention
The present invention relates generally to non-volatile memory devices (“flash memory devices”) and, more particularly, to independently controlling a read voltage (or a program-verify voltage) and temperature co-efficient associated with the voltage
2. Background of the Invention
Semiconductor memory devices have become popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other electronic devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
One example of a flash memory system uses the NAND structure, which includes arranging multiple transistors in series, sandwiched between two select gates. A NAND array has a number of memory cells (or storage units, used interchangeably throughout this specification), such as 4, 8, 16, or even 32, connected in series string (NAND string) between a bit line and a reference potential through select transistors at either end. Word lines are connected with control gates of cells in different series strings. Relevant examples of NAND arrays and their operation are given in the following U.S. patents that are incorporated herein in their entirety by this reference: U.S. Pat. Nos. 5,570,315, 5,774,397 and 6,046,935.
Individual memory cells of such flash memory devices typically include one or more storage elements that store a variable amount of static charge. The storage elements are most commonly conductive floating gates, so this is the example primarily described herein, but can also be areas of a charge trapping dielectric. The level of charge stored by the floating gate represents the data value stored by the data storage element. The floating gate typically overlies a channel region of a transistor.
Data is read from a storage location by applying a voltage to a control gate overlying the floating gate. The level of charge stored by the floating gate, in combination with the voltage applied to the control gate, determines whether the transistor will conduct current through its channel. The level of charge stored by the floating gate can therefore be determined by either measuring that current or finding the control gate voltage required to make the transistor conduct. In either case, the measured quantity is compared with reference levels in order to determine the state of the cells.
Binary state memory cells may be used in flash memories. These memory cells have two states: “programmed” (usually representing a one) and “erased” (usually representing a zero). However, such cells do not efficiently use the valuable real estate of the integrated circuit, since only one bit of information is stored per floating gate. Many flash memories therefore use multiple charge levels (more than two) for the floating gates, so that each floating gate may store more than one bit of information.
As the number of charge level states of the operation of individual floating gates increases, the voltage difference between the states necessarily decreases. The increasing proximity of the voltage level ranges for an increased number of states makes discerning one state from another difficult.
Since the operating characteristics of the memory cell transistors change with temperature, the control gate voltage required to turn on the transistor also should vary with temperature, even as the charge level carried by the floating gate remains unchanged. Any mismatch in the thermal variation of the control gate voltage and the thermal variation of the operating characteristics of the memory cell transistors can result in inaccurate reading of data from memory cells, due to the close proximity of the voltage levels of the floating gate.
During a read or program-verify operation of a multilevel memory cell (MLC) a plurality of predetermined voltages are applied from a voltage generator to the control gate of the selected memory cell. A resulting threshold voltage Vt varies with temperature, which is denoted by a temperature coefficient. Temperature coefficient is a temperature dependent multiplication factor. In flash memories the threshold voltage temperature co-efficient (TCO) has a typical value of approximately −1.7 mV/° C. The intrinsic TCO value of a memory cell can vary from −1.2 mV/° C. to −2.2 mV/° C.
Data is stored in a memory cell at one temperature and may be read at another temperature. The read voltage applied to a memory cell gate should be greater than the threshold voltage of the memory cell and this difference should remain substantially constant over a temperature. Thus, it is desirable that the TCO for various voltages applied to the memory cell be substantially similar to the intrinsic TCO of the memory cell.
Conventional systems fail to independently control the voltage level and the TCO. This has disadvantages because the TCO of the memory cell may not match the TCO of the applied voltage. Conventional systems fail to adjust the TCO to compensate for variations in the memory cells intrinsic TCO and/or compensate for variations in the circuits that generate the TCO.
Conventional systems fail to efficiently trim TCO values during flash memory testing.
Therefore, there is a need for a system and method to efficiently/independently control the applied voltage level and TCO and efficiently trim TCO values during flash memory testing.